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ISL84781
Data Sheet November 17, 2004 FN6095.2
Ultra Low ON-Resistance, Low-Voltage, Single Supply, 8 to 1 Analog Multiplexer
The Intersil ISL84781 device contains precision, bidirectional, analog switches configured as an 8 channel multiplexer/demultiplexer. It is designed to operate from a single +1.6V to +3.6V supply. The device has an inhibit pin to simultaneously open all signal paths. ON resistance is 0.4 with a +3.0V supply and 0.55 with a single +1.8V supply. Each switch can handle rail to rail analog signals. The off-leakage current is only 4nA max at +25C or 40nA max at +85C with a +3.3V supply. All digital inputs are 1.8V logic-compatible when using a single +3V supply. The ISL84781 is a 8 to 1 multiplexer device that is offered in a 16 Ld TSSOP package, and a 16 Ld thin QFN package. Table 1 summarizes the performance of this family.
TABLE 1. FEATURES AT A GLANCE ISL84781 Configuration 3V RON 3V tON/tOFF 1.8V RON 1.8V tON/tOFF Packages 8:1 Mux 0.4 16ns/13ns 0.55 24ns/16ns 16 Ld TSSOP, 16 Ld 3x3 thin QFN
Features
* Pin Compatible Replacement for the MAX4781, and MAX4617 * ON Resistance (RON) - V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 - V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.55 * RON Matching Between Channels. . . . . . . . . . . . . . . . 0.12 * RON Flatness Across Signal Range . . . . . . . . . . . . . .0.056 * Single Supply Operation. . . . . . . . . . . . . . . . . +1.6V to +3.6V * Low Power Consumption (PD). . . . . . . . . . . . . . . . . . <0.2W * Fast Switching Action (VS = +3V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13ns * Guaranteed Break-Before-Make * High Current Handling Capacity (300mA Continuous) * Available in 16 Ld TSSOP and 16 Ld 3x3 Thin QFN * 1.8V CMOS-Logic Compatible (+3V Supply) * Pb-Free Available as an Option (RoHS Compliant) (see Ordering Info) * ISL84781IR Replaces the ISL43L680IR.
Applications
* Battery Powered, Handheld, and Portable Equipment - Cellular/Mobile Phones - Pagers - Laptops, Notebooks, Palmtops * Portable Test and Measurement * Medical Equipment * Audio Switching and Routing
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" * Application Note AN557 "Recommended Test Procedures for Analog Switches"
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL84781 Pinouts
(Note 1) ISL84781IV (TSSOP) TOP VIEW ISL84781IR (3x3 THIN QFN) TOP VIEW
NO6 NO4 NO2 13 12 NO1 11 NO0 10 NO3 9 5 N.C. 6 GND 7 ADD2 8 ADD1 ADD0 V+ 14
NO4 1 NO6 2 COM 3 NO7 4 NO5 5 INH 6 N.C. 7 GND 8 LOGIC
16 V+ 15 NO2 14 NO1 13 NO0 12 NO3 11 ADD0 10 ADD1 9 ADD2 COM NO7 NO5 INH 1 2 3 4
16
15
NOTE: 1. Switches Shown for Logic "0" Inputs.
Truth Table
ISL84781 INH 1 0 0 0 0 0 0 0 0 NOTE: Care. ADD2 X 0 0 0 0 1 1 1 1 ADD1 X 0 0 1 1 0 0 1 1 ADD0 X 0 1 0 1 0 1 0 1 SWITCH ON NONE NO0 NO1 NO2 NO3 NO4 NO5 NO6 NO7
Ordering Information
PART NO. ISL84781IV ISL84781IV-T ISL84781IR ISL84781IR-T TEMP. RANGE (C) -40 to 85 -40 to 85 -40 to 85 -40 to 85 PACKAGE 16 Ld TSSOP 16 Ld TSSOP Tape & Reel 16 Ld 3x3 Thin QFN 16 Ld 3x3 Thin QFN Tape & Reel 16 Ld TSSOP (Pb-free) 16 Ld TSSOP Tape and Reel (Pb-free) 16 Ld 3x3 Thin QFN (Pb-free) 16 Ld 3x3 Thin QFN Tape and Reel (Pb-free) PKG. DWG. # M16.173 M16.173 L16.3x3A L16.3x3A
ISL84781IVZ (See Note) ISL84781IVZ-T (See Note) ISL8478IRZ (See Note)
-40 to 85 -40 to 85
M16.173 M16.173
Logic "0" 0.5V. Logic "1" 1.4V, with a 3V supply. X = Don't -40 to 85
L16.3x3A
Pin Descriptions
PIN V+ N.C. GND INH COM NO0 NO7 ADD FUNCTION System Power Supply Input (1.6V to 3.6V) No Connect. Not internally connected. Ground Connection Digital Control Input. Connect to GND for Normal Operation. Connect to V+ to turn all switches off. Analog Switch Common Pin Analog Switch Input Pin Address Input Pin
ISL8478IRZ-T (See Note)
-40 to 85
L16.3x3A
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
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FN6095.2 November 17, 2004
ISL84781
Absolute Maximum Ratings
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V Input Voltages INH, NO, ADD (Note 2) . . . . . . . . . . . . . . . . . -0.3 to (V+) + 0.3V Output Voltages COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (V+) + 0.3V Continuous Current NO or COM . . . . . . . . . . . . . . . . . . . . . 300mA Peak Current NO or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . 500mA ESD Rating HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4kV MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300V CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1000V
Thermal Information
Thermal Resistance (Typical, Note 3) JA (C/W) 16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 150 16 Ld 3x3 Thin QFN Package . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature (Plastic Package). . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300C (Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 2. Signals on NO, COM, ADD, or INH exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 3V Supply Test Conditions: VSUPPLY = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 8),
Unless Otherwise Specified TEST CONDITIONS TEMP (C) Full V+ = 2.7V, ICOM = 100mA, VNO = 0V to V+, (See Figure 5) V+ = 2.7V, ICOM = 100mA, VNO = Voltage at max RON, (Note 6) V+ = 2.7V, ICOM = 100mA, VNO = 0V to V+, (Note 7 V+ = 3.3V, VCOM = 0.3V, 3V, VNO = 3V, 0.3V, (Note 8) V+ = 3.3V, VCOM = VNO = 0.3V, 3V, (Note 8) 25 Full 25 Full 25 Full 25 Full 25 Full Full Full V+ = 3.6V, VINH = VADD = 0V or V+ (Note 9) Full (NOTE 5) MIN 0 -4 -40 -15 -70 1.4 -0.5 (NOTE 5) MAX UNITS V+ 0.75 0.8 0.2 0.2 0.15 0.15 4 40 15 70 0.5 0.5 V nA nA nA nA V V A
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON RON Matching Between Channels, RON RON Flatness, RFLAT(ON) NO OFF Leakage Current, INO(OFF) COM ON Leakage Current, ICOM(ON)
TYP 0.41 0.12 0.056 -
DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINH, VADDH Input Voltage Low, VINL, VADDL Input Current, IINH, IINL, IADDH, IADDL DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON Inhibit Turn-OFF Time, tOFF Address Transition Time, tTRANS Break-Before-Make Time, tBBM Charge Injection, Q Input OFF Capacitance, COFF V+ = 2.7V, VNO = 1.5V, RL = 50, CL = 35pF, (See Figure 1, Note 9) V+ = 2.7V, VNO = 1.5V, RL = 50, CL = 35pF, (See Figure 1, Note 9) V+ = 2.7V, VNO = 1.5V, RL = 50, CL = 35pF, (See Figure 1, Note 9) V+ = 3.3V, VNO = 1.5V, RL = 50, CL = 35pF, (See Figure 3, Note 9) CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) f = 1MHz, VNO = VCOM = 0V, (See Figure 6) 25 Full 25 Full 25 Full 25 Full 25 25 1 16 14 19 4 -39 65 25 27 23 25 28 30 ns ns ns ns ns ns ns ns pC pF
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FN6095.2 November 17, 2004
ISL84781
Electrical Specifications - 3V Supply Test Conditions: VSUPPLY = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 8),
Unless Otherwise Specified (Continued) TEST CONDITIONS f = 1MHz, VNO = VCOM = 0V, (See Figure 6) f = 1MHz, VNO = VCOM = 0V, (See Figure 6) RL = 50, CL = 35pF, f = 100kHz, (See Figure 4) f = 20Hz to 20kHz, 0.5Vp-p, RL = 32 TEMP (C) 25 25 25 25 Full V+ = 3.6V, VINH, VADD = 0V or V+, Switch On or Off 25 Full NOTES: 4. VIN = Input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. RON matching between channels is calculated by subtracting the channel with the highest max Ron value from the channel with lowest max Ron value. 7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 8. Parts are 100% tested at +25C. Limits across the full temperature range are guaranteed by design and correlation. 9. Guaranteed but not tested. (NOTE 5) MIN 1.6 (NOTE 5) MAX UNITS 3.6 0.05 1.2 pF pF dB % V A A
PARAMETER COM OFF Capacitance, COFF COM ON Capacitance, CCOM(ON) OFF Isolation Total Harmonic Distortion (THD) Power Supply Range Positive Supply Current, I+
TYP 470 485 65 0.014 -
POWER SUPPLY CHARACTERISTICS
Electrical Specifications: 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Notes 4, 8),
Unless Otherwise Specified TEST CONDITIONS TEMP (C) MIN (NOTE 5) MAX (NOTE 5) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
TYP
Full V+ = 1.8V, ICOM = 10.0mA, VNO = 1.0V, (See Figure 5) V+ = 1.8V, ICOM = 10.0mA, VNO = 1.0V, (See Figure 5) V+ = 1.8V, ICOM = 10.0mA, VNO = 0V, 0.9V, 1.6V, (See Figure 5) 25 Full 25 Full 25 Full
0 -
0.55 0.1 0.13 0.14 0.16
V+ 0.85 0.9 -
V
RON Matching Between Channels, RON) RON Flatness, RFLAT(ON)
DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINH, VADDH Input Voltage Low, VINL, VADDL Input Current, IINH, IINL, IADDH, IADDL DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON V+ = 1.8V, VNO = 1.0V, RL = 50, CL = 35pF, (See Figure 1, Note 9) V+ = 1.8V, VNO = 1.0V, RL = 50, CL = 35pF, (See Figure 1, Note 9) V+ = 1.8V, VNO = 1.0V, RL = 50, CL = 35pF, (See Figure 1, Note 9) V+ = 1.8V, VNO = 1.0V, RL = 50, CL = 35pF, (See Figure 3, Note 9) CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) 25 Full 25 Full 25 Full 25 25 24 16 25 9 -20 33 35 25 27 34 36 ns ns ns ns ns ns ns pC V+ = 1.8V, VINH, VADD = 0V or V+ (Note 9) Full Full Full 1 -0.5 0.4 0.5 V V A
Inhibit Turn-OFF Time, tOFF
Address Transition Time, tTRANS
Break-Before-Make Time, tBBM Charge Injection, Q
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FN6095.2 November 17, 2004
ISL84781 Test Circuits and Waveforms
C V+ LOGIC INPUT 0V tON 50% tr < 5ns tf < 5ns VNO0 NO0 NO1-NO7 INH VNO0 SWITCH OUTPUT 90% VOUT 90% LOGIC INPUT COM VOUT V+ C
GND ADD2-0
RL 50
CL 35pF
0V tOFF
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for other switches. CL includes fixture and stray capacitance. RL V OUT = V NOx -----------------------------R L + R ( ON ) FIGURE 1B. INHIBIT tON/tOFF TEST CIRCUIT
FIGURE 1A. INHIBIT tON/tOFF MEASUREMENT POINTS
V+ LOGIC INPUT 50% 0V tTRANS
tr < 5ns tf < 5ns
C
V+
C
VNO0
NO0 NO1-NO7 COM INH VOUT
VNO0 SWITCH OUTPUT VNO7 tTRANS
VOUT
90%
ADD2-0 GND LOGIC INPUT
RL 50
CL 35pF
10% 0V
Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 1C. ADDRESS tTRANS MEASUREMENT POINTS
Repeat test for other switches. CL includes fixture and stray capacitance. RL -----------------------------V OUT = V NOx R + R L ( ON ) FIGURE 1D. ADDRESS tTRANS TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
C
V+ LOGIC INPUT OFF ON 0V 0 SWITCH OUTPUT VOUT Q = VOUT x CL VOUT VG CHANNEL SELECT ADD2 ADD1 ADD0 GND INH LOGIC INPUT OFF RG VOUT NOx COM
CL 1000pF
FIGURE 2A. Q MEASUREMENT POINTS
Repeat test for other switches. FIGURE 2B. Q TEST CIRCUIT FIGURE 2. CHARGE INJECTION
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FN6095.2 November 17, 2004
ISL84781 Test Circuits and Waveforms (Continued)
V+ C V+ LOGIC INPUT 0V tr < 5ns tf < 5ns VNOx NO0-NO7 ADD2-0 COM RL 50 CL 35pF C
VOUT
SWITCH OUTPUT
90% VOUT 0V tBBM
LOGIC INPUT GND INH
Repeat test for other switches. CL includes fixture and stray capacitance. FIGURE 3A. tBBM MEASUREMENT POINTS FIGURE 3B. tBBM TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
V+
10nF
V+
C
SIGNAL GENERATOR
NOx
RON = V1/100mA NOx ADD2 ADD1 ADD0 0V or V+ VNX 100mA
CHANNEL SELECT
V1
0V or V+ ADD2 ADD1 ADD0 COM GND INH
ANALYZER RL
COM
0V or V+ GND INH
CHANNEL SELECT
Off-Isolation is measured between COM and "Off" NO terminal on each switch. Signal direction through switch is reversed and worst case values are recorded. FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. RON TEST CIRCUIT
V+
C
NOx
1MHz IMPEDANCE ANALYZER COM
0V or V+ ADD2 ADD1 ADD0
Channel Select
GND
INH
FIGURE 6. CAPACITANCE TEST CIRCUIT
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FN6095.2 November 17, 2004
ISL84781 Detailed Description
The ISL84781 analog multiplexer offers precise switching capability from a single 1.6V to 3.6V supply with ultra low onresistance (0.41) and high speed operation (tON = 16ns, tOFF = 13ns) with +3V supply. The device is especially wellsuited for portable battery powered equipment thanks to the low operating supply voltage (1.6V), low power consumption (0.2W), and low leakage currents (70nA max). High frequency applications also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection.
Power-Supply Considerations
The ISL84781 construction is typical of most single supply CMOS analog multiplexers, in that it has two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set its analog voltage limits. Unlike switches with a 4V maximum supply voltage, the ISL84781 4.7V maximum supply voltage provides plenty of room for the 10% tolerance of 3.6V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.6V but the part will operate with a supply below 1.5V. It is important to note that the input signal range, switching times, and onresistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance curves for details. V+ and GND power the internal logic and level shifters. The level shifters convert the logic levels to switched V+ and GND signals to drive the analog switch gate terminals. These multiplexers cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (See Figure 7). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1k resistor in series with the input (see Figure 7). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not applicable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low RON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 7). These additional diodes limit the analog signal from 1V below V+ to 1V above GND. The low leakage current performance is unaffected by this approach, but the switch signal range is reduced and the resistance may increase, especially at low supply voltages.
OPTIONAL PROTECTION RESISTOR FOR LOGIC INPUTS V+
Logic-Level Thresholds
This device is 1.8V CMOS compatible (0.5V and 1.4V) over a supply range of 2.0V to 3.6V (See Figure 12). At 3.6V the VIH level is about 1.27V. This is still below the 1.8V CMOS guaranteed high output minimum level of 1.4V, but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation.
High-Frequency Performance
In 50 systems, signal response is reasonably flat even past 10MHz with a -3dB bandwidth of 52MHz (See Figure 16). The frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch's input to its output. Off Isolation is the resistance to this feed through. Figure 17 details the high Off Isolation provided by these devices. At 100kHz, Off Isolation is about 65dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation due to the voltage divider action of the switch OFF impedance and the load impedance.
OPTIONAL PROTECTION DIODE
1k
LOGIC VNOx VCOM
GND OPTIONAL PROTECTION DIODE
Leakage Considerations
Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND.
FN6095.2 November 17, 2004
FIGURE 7. OVERVOLTAGE PROTECTION
7
ISL84781
Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND.
Typical Performance Curves TA = 25C, Unless Otherwise Specified
0.75 ICOM = 100mA 0.7 V+ = 1.65V 0.65 0.6 RON () 0.55 0.5 0.45 V+ = 2.7V 0.4 0.35 V+ = 3V V+ = 3.6V 0 1 2 VCOM (V) 3 4 V+ = 1.8V RON () 0.5 85C 0.45 0.55 V+ = 3V ICOM = 100mA
0.4
25C
0.35 -40C 0.3 0 0.5 1 1.5 VCOM (V) 2 2.5 3
FIGURE 8. ON RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
FIGURE 9. ON RESISTANCE vs SWITCH VOLTAGE
0.7 0.65 0.6 0.55 RON () 0.5
-10 V+ = 1.8V ICOM = 100mA -20 -30 -40 85C -50 -60 Q (pC) 25C -70 -80 -90 -40C -100 -110 -120 0 0.5 1 VCOM (V) 1.5 2 0 0.5 1 1.5 VCOM (V) 2 2.5 3 V+ = 3V V+ = 1.8V
0.45 0.4 0.35 0.3
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 11. CHARGE INJECTION vs SWITCH VOLTAGE
8
FN6095.2 November 17, 2004
ISL84781 Typical Performance Curves TA = 25C, Unless Otherwise Specified (Continued)
1.6 60
1.4 50 VINH AND VINL (V) 1.2 tRANS (ns) VINL VINH 1 40
0.8
30 85C 20 25C
0.6
-40C
1
1.5
2
2.5 V+ (V)
3
3.5
4
4.5
10
1
1.5
2
2.5 3 V+ (V)
3.5
4
4.5
FIGURE 12. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FIGURE 13. ADDRESS TRANS TIME vs SUPPLY VOLTAGE
25
60
50 20 tOFF (ns) tON (ns) 40 85C 25C 15 -40C 20 -40C
30
85C
25C
10
10 1 1.5 2 2.5 3 V+ (V) 3.5 4 4.5
1
1.5
2
2.5 V+ (V)
3
3.5
4
4.5
FIGURE 14. INHIBIT TURN-ON TIME vs SUPPLY VOLTAGE
NORMALIZED GAIN (dB)
FIGURE 15. INHIBIT TURN-OFF TIME vs SUPPLY VOLTAGE
0 V+ = 3V -10 -20 OFF ISOLATION (dB) -30 -40 -50 ISOLATION -60 -70 -80 -90 -100 1k 10k 100k 1M 10M 70 80 90 100 110 100M 500M 20 30 40 50 60 10
V+ = 3V 0 -10 GAIN
PHASE
0 20 40 60 80 PHASE (DEGREES)
RL = 50 VIN = 0.2VP-P to 2VP-P 0.1 1 10 FREQUENCY (MHz)
100 100
FREQUENCY (Hz)
FIGURE 16. FREQUENCY RESPONSE
FIGURE 17. OFF ISOLATION
9
FN6095.2 November 17, 2004
ISL84781 Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): GND (QFN Paddle Connection: To Ground or Float) TRANSISTOR COUNT: 228 PROCESS: Submicron CMOS
10
FN6095.2 November 17, 2004
ISL84781 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 L 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 GAUGE PLANE 0.25(0.010) M BM
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.033 0.0075 0.0035 0.193 0.169 MAX 0.043 0.006 0.037 0.012 0.008 0.201 0.177 MILLIMETERS MIN 0.05 0.85 0.19 0.09 4.90 4.30 MAX 1.10 0.15 0.95 0.30 0.20 5.10 4.50 NOTES 9 3 4 6 7 8o Rev. 1 2/02
A1 0.10(0.004) A2 c
E1 e E L N
e
b 0.10(0.004) M C AM BS
0.026 BSC 0.246 0.020 16 0o 8o 0.256 0.028
0.65 BSC 6.25 0.50 16 0o 6.50 0.70
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AB, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
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FN6095.2 November 17, 2004
ISL84781 Thin Quad Flat No-Lead Plastic Package (TQFN) Thin Micro Lead Frame Plastic Package (TMLFP)
)
2X 0.15 C A A 9 D1 D1/2 6 INDEX AREA N 1 2 3 E1/2 E1 9 2X 0.15 C B 2X 0.15 C A 4X 0 TOP VIEW A2 A / / 0.10 C 0.08 C SEATING PLANE SIDE VIEW NX b 4X P D2 (DATUM B) 4X P 1 (DATUM A) 6 INDEX AREA NX L Ne 8 (Nd-1)Xe REF. BOTTOM VIEW A1 NX b 5 2 3 E2 7 E2/2 8 (Ne-1)Xe REF. D2 2N 5 0.10 M C A B 7 8 NX k A3 A1 B E/2 E 2X 0.15 C B D D/2
L16.3x3A
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L N Nd Ne P 1.35 0.20 0.30 1.35 0.18 MIN 0.70 NOMINAL 0.75 0.20 REF 0.23 3.00 BSC 2.75 BSC 1.50 3.00 BSC 2.75 BSC 1.50 0.50 BSC 0.40 16 4 4 0.60 12 0.50 1.65 1.65 0.30 MAX 0.80 0.05 0.80 NOTES 9 9 5, 8 9 7, 8, 10 9 7, 8, 10 8 2 3 3 9 9 Rev. 0 6/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance.
C
9
9 CORNER OPTION 4X
SECTION "C-C" C L C L
8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
L1 e 10 L
L1 CC e
10
L
9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Compliant to JEDEC MO-220WEED-2 Issue C, except for the E2 and D2 MAX dimension.
TERMINAL TIP FOR EVEN TERMINAL/SIDE
FOR ODD TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN6095.2 November 17, 2004

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